Random telegraph signals in semiconductor devices /

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"Version: 20161001"--Title page verso.Includes bibliographical references.4. Impact device processing and scaling on RTS -- 4.1. Processing effects on RTS -- 4.2. RTS in fin-type architectures -- 4.3. Nanometric scaling aspects of RTS -- 4.4. RTS in 'beyond-silicon' devices5. Operational and reliability aspects of RTS -- 5.1. Switching AC operation of RTS -- 5.2. Impact of uniform and HC degradation -- 5.3. BTI and RTS: oxide trapping? -- 5.4. Statistical RTS measurement methods -- 5.5. Device and circuit simulation of dynamic variability6. RTS in memory and imager circuits -- 6.1. RTS in flash and SRAM cells -- 6.2. RTS in DRAM and logic circuits -- 6.3. RTS in novel ReRAM and PCMs -- 6.4. RTS in CMOS imagers and CCDs -- 7. General conclusions.Preface -- 1. Introduction2. Random telegraph signal phenomenology -- 2.1. RTS time constants -- 2.2. RTS amplitude behavior -- 2.3. RTS in the gate current of a MOS device -- 2.4. RTS in the junction leakage current of a MOSFET -- 2.5. Multiple and complex3. RTS modeling, simulation and parameter extraction -- 3.1. Time constant modeling and simulation -- 3.2. Extraction trap position from RTS time constants -- 3.3. RTS amplitude modeling -- 3.4. Atomistic numerical modeling of the RTS amplitude -- 3.5. Novel measurement and analysis methods -- 3.6. Ab initio modeling of RTS in gate dielectricsFollowing their first observation in 1984, random telegraph signals (RTSs) were initially a purely scientific tool to study fundamental aspects of defects in semiconductor devices. As semiconductor devices move to the nanoscale however, RTSs have become an issue of major concern to the semiconductor industry, both in development of current technology, such as memory devices and logic circuits, as well as in future semiconductor devices beyond the silicon roadmap, such as nanowire, TFET and carbon nanotube-based devices. It has become clear that the reliability of state-of-the-art and future CMOS technology nodes is dominated by RTS and single trap phenomena, and so its understanding is of vital importance for the modelling and simulation of the operation and the expected lifetime of CMOS devices and circuits. It is the aim of this book to provide a comprehensive and up-to-date review of one of the most challenging issues facing the semiconductor industry, from the fundamentals of RTSs to applied technology.Researcher, practitioner.Also available in print.Mode of access: World Wide Web.System requirements: Adobe Acrobat Reader.Eddy Simoen is Senior Researcher at imec and Professor at Ghent University, Belgium. Cor Claeys is Director of Advanced Semiconductor Technologies at imec, and Professor at KU Leuven, Belgium.Title from PDF title page (viewed on November 2, 2016).

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Publisher

: .,

Collation

1 online resource (various pagings) :illustrations (some color).

Language

English

ISBN/ISSN

9780750312721

Classification

621.3815/2

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-

Subject(s)

SCIENCE / Nanoscience.
SCIENCE / Physics / Condensed Matter.
Electronic devices & materials.
Electricity, electromagnetism and magnetism.
Semiconductors

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Statement of Responsibility

Eddy Simoen, Cor Claeys.

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